1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, to an ultrasonic flip chip bonding technique of packaging a flip chip.
2. Description of the Related Art
In an ultrasonic flip chip bonding technique, a printed circuit board is chucked by a heatable fixing jig called a stage. A semiconductor chip (semiconductor element) is packaged while being chucked by an apparatus having a pressure & ultrasonic application mechanism called a tool or a mechanism also using heating. At this time, the element formation surface of the semiconductor chip and the wiring electrode formation surface of the printed circuit board are faced to each other in order to bond a stud bump formed on the electrode of the semiconductor chip and a plated bump or stud bump formed on the wiring electrode of the printed circuit board. While ultrasonic waves are applied from the tool to the semiconductor chip, a load is also applied. In some cases, the semiconductor chip and printed circuit board are bonded while the tool or stage is heated to heat either or both of the semiconductor chip and printed circuit board, in addition to application of ultrasonic waves and the load.
A flip chip process using ultrasonic waves and an apparatus therefor are disclosed in, e.g., U.S. Pat. No. 5,427,301.
In the conventional semiconductor device manufacturing method, a bump formed on the electrode of a semiconductor chip does not uniformly contact a wiring electrode on the printed circuit board in case of insufficient parallelism adjustment between the tool and the stage or insufficient perpendicularity of the bonding surfaces of the tool and stage in the pressure direction of the tool. Thus, the stress concentrates on a bump which first contacts the wiring electrode. The bump readily peels or misaligns from the wiring electrode, and is bonded again to the electrode of the semiconductor chip at the misaligned position. This bonding state is less reliable, and the bump may come off the electrode of the semiconductor chip in the worst case.
To improve the connectivity and reliability in the ultrasonic flip chip bonding technique, adjustment of the parallelism and perpendicularity of the tool and stage is important. However, these adjustments require a precision of several μm, are very difficult, and take about 2 hours regardless of any state-of-the-art apparatus.
Recently, strong demands have arisen for thinner semiconductor chips in order to incorporate a semiconductor chip into, e.g., a card-like thin package. To meet this demand, the lower surface of a semiconductor wafer is ground and etched to 100 μm or less. However, a semiconductor chip as thin as 100 μm or less is damaged by ultrasonic vibrations in flip chip connection, generating a defect such as a scratch or crack.
To chuck a semiconductor chip, a chuck hole is formed in the tool for evacuation. When a sealing resin layer is interposed between a semiconductor chip and a printed circuit board and simultaneous flip chip connection including the sealing step is performed, the semiconductor chip deforms due to the resin stress concentrated in the chuck hole because of a thin semiconductor chip, damaging the semiconductor chip. For this reason, a load enough for bonding cannot be applied between the semiconductor chip and the printed circuit board.
As a measure to solve this problem, the pressure is applied for connection using a flat tool having no chuck hole after temporary fixing by low-pressure alignment. Alternatively, a semiconductor chip is chucked by porous chucking. However, the former method increases the number of manufacturing steps, whereas the latter method decreases the tool durability by ultrasonic vibrations. Either method is not a permanent measure.
As described above, it is difficult for the conventional semiconductor device manufacturing method to improve the connectivity. A thin semiconductor chip may be damaged in flip chip connection.